1. Field of the Invention
The present invention relates to a semiconductor device provided with a circuit for utilizing electric charge which has become unnecessary on a complementary signal line pair.
2. Description of the Related Art
FIG. 8(A) shows a circuit associated with hierarchical bit-line structure in a prior art DRAM.
A local bit-line pair LBL11 and *LBL11 are connected via transfer gates 10 and 11 to a global bit-line pair GBL1 and *GBL1, respectively. In addition, a local bit-line pair LBL12 and *LBL12 are connected thereto via transfer gates 20 and 21, respectively. A reset voltage VR is applied to each of the local bit-line pair LBL11 and *LBL11 via reset switches 12 and 13, respectively, while a reset voltage VR is applied to each of the local bit-line pair LBL12 and *LBL12 via reset switches 22 and 23, respectively. A sense amplifier 30 and a global bit-line resetting circuit 31 are connected between the global bit-line pair GBL1 and *GBL1.
MC1 through MC8 are memory cells, and FIG. 8(A) shows a case where only two memory cells are connected to each of the local bit-lines for simplification. As shown in FIG. 8 (B), in a memory cell, a transfer gate is connected to a capacitor in series, wherein one electrode of the capacitor is connected to a plate of the reset voltage VR.
A local block LB1 containing memory cells MC1 through MC4 and another local block LB2 containing memory cells MC5 through MC8 are not activated at the same time.
For example, in a case where the content of the memory cell MC1 is read out, as a initial state, the reset circuit 31 is on, whereby the global bit-line pair GBL1 and *GBL1 are precharged at the reset voltage VR, the transfer gates 10, 11, 20 and 21 are off and the reset switches 12, 13, 22 and 23 are on, whereby the local bit-line pairs LBL11, *LBL11 and LBL12, *LBL12 are precharged at the reset voltage VR.
From this state, the reset circuit 31, and reset switches 12 and 13 are turned off, the transfer gates 10 and 11 are turned on, and the word line WL1 is raised to read out the content of the memory cell MC1, whereby a voltage difference of about 0.2V between the global bit-line pair GBL1 and *GBL1 arises. This difference is amplified by the sense amplifier 30.
With such a hierarchical bit-line structure, since the number of memory cells simultaneously conducted to the global bit-line pair GBL1 and *GBL1 is decreased and thereby parasitic capacity is reduced, the memory access becomes faster, and further a power consumption is reduced. Furthermore, since the number of memory cells per sense amplifier 30 is increased, higher integration is enabled.
The transfer gates 10 through 13 and 20 through 23 are composed of NMOS transistors, same as those in the transfer gates of the memory cells, to achieve higher integration density. Therefore, in order to turn on each transfer gate, it is necessary to make the gate electrode voltage greater than the value which is the sum of the threshold voltage Vth and source voltage of the transfer gate. For example, if the maximum value VC of the source voltage is 2.5V and the Vth is 1.5V, the gate voltage SVC to turn on the transfer gate is 4.0 or more.
The transfer gates 10 and 11 are turned on and off together with the other transfer gates connected to other global bit-lines (not shown) in the same local block. This is the same as to the reset switches 12 and 13. The on and off of the transfer gates 10 and 11 are the inverse of the on and off of the reset switches 12 and 13.
Therefore, a pair of mutually complementary LBL (Local Bit Line) selection signal .0.S1 and LBL-reset signal .0.R1 are generated at a local bit-line control circuit 14, where .0.S1 is made with boosting a HIGH of a local block selection signal .0.A1 and further amplifying its driving capacity, and the transfer gates 10, 11 and so forth are on-off controlled with the LBL signal .0.S1, and the reset switches 12, 13 and so forth are on-off controlled with the LBL-reset signal .0.R1. A local bit-line control circuit 24 for the local block LB2 is the same structure as the local bit-line control circuit 14 for the local block LB1.
FIG. 9 shows a structure of the local bit-line control circuit 14.
A level shift circuit 141 generates, in response to a local block selection signal .0.A1, mutually complementary signals .0.A1V and *.0.A1V, where .0.A1V is made with boosting a HIGH of .0.A1 from a supply voltage VC to a supply voltage SVC. A drive circuit 142A inverts the logic state of the signal *.0.A1V and further amplifies its driving capacity to make the LBL-selection signal .0.S1, while a drive circuit 142B inverts the logic state of the signal .0.A1V and further amplifies its driving capacity to make the LBL-reset signal .0.R1.
In this way, since it is necessary to turn on and off a number of NMOS transistors at the same time after boosting a HIGH voltage and further amplifying it at the local bit-line control circuit 14, for example, a current consumption of the local bit-line control circuit becomes 20 mA through 30 mA in a 256 MB DRAM. Such a problem will occur in a semiconductor device provided with a similar circuit.